People
Project Lecturer
No image available Mr. Rajeev Kumar
M.Tech (Kurukshetra University). B. Tech (AMIETE), MSc. Electronics (B.U Jhansi)
E-mail : [email protected], [email protected]
Research Interests : Architecture design for Image Processing based system, Low Power VLSI design and FPGA.
Project Engineer
No image available Mr. Rajesh Saha
Pursuing Ph.D. (NIT UK), M. Tech (NIT Arunachal Pradesh).
E-mail : [email protected], [email protected]
Research Interests : Digital System Design, FPGA, Low power memory Design, spintronic, Linux scripting and EDA tools.
Project Staff
News & Announcement

1. PRSG meeting to be held in the month of Nov/Dec, 2019

2. CEERI, Nodal Agency and Meity asked for UC-FY-2018-19 and to be submitted around 2nd week of September, 2019.

3. PRSG meeting-VI held at MeitY Delhi, Which attend by Dr. Pankaj Kr. Pal and Rajesh Saha. They presented the progress of the Project to RC and MeitY in the month of June/July, 2017.

4. Six Monthly FY and Technical report with Utilization Certificate (July-Dec, 2018) sent to CEERI Pilani and MeitY.
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